One of the steps in the synthesis of logic circuits on an integrated circuit is the optimization of timing paths, in particular, the optimization of setup and hold times on sequential circuits. For a typical register in a sequential logic circuit having a data input and clock input, the data input generally needs to be in a stable state before, during and after the clock transition in order to register to successfully clock the data input. The time during which the data needs to be held prior to the clock transition is the setup constraint, and the time during which the data needs to be held after the clock transition is the hold constraint.
Ensuring that a particular logic design meets all setup and hold constraints is generally performed using a computer aided timing optimization tool, which first performs a timing analysis taking into account device and gate characteristics and layout parasitics. The timing optimization tool then inserts a delay buffer immediately prior to a data input of a latch or register that violates a hold constraint. By delaying the data signal, the delay buffer delays a signal transition long enough so that the hold constraint is met. Such an approach is suitable for simple designs, for example, a data register having a single incoming data path.
In more topologically complex designs, for example, where a register input has multiple paths and sources, timing optimization becomes more challenging. If a logic path to a single register input has two input paths, for example, a short delay path and a long delay path where the transition edge arrives earlier for the short delay path than for the long delay path, inserting a delay buffer to compensate for the a violation of the hold constraint for the short delay path may violate the setup constraint for the long delay path.
What is needed are systems and methods of optimizing timing paths of sequential circuits.